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Low-noise wideband PLL with dual-mode ring-VCO.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 9/30/2010, Vol. 46 Issue 20, p1368-1370, 3p, 2 Diagrams, 3 Graphs
- Publication Year :
- 2010
-
Abstract
- A low-jitter 110 MHz-to-620 MHz phase-locked loop (PLL) that includes a low-noise wide-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65 nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5 ps RMS jitter at 600 MHz of output frequency while consuming 2.7 mW at a 1.2 V supply. The die area is only 0.09 mm2. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 46
- Issue :
- 20
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 53980561
- Full Text :
- https://doi.org/10.1049/el.2010.2028