Cite
Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic.
MLA
Kam, Hei, et al. “Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic.” IEEE Transactions on Electron Devices, vol. 58, no. 1, Jan. 2011, pp. 236–50. EBSCOhost, https://doi.org/10.1109/TED.2010.2082545.
APA
Kam, H., Liu, T.-J. K., Stojanovi, , Vladimir, Markovic, D., & Alon, E. (2011). Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic. IEEE Transactions on Electron Devices, 58(1), 236–250. https://doi.org/10.1109/TED.2010.2082545
Chicago
Kam, Hei, Tsu-Jae King Liu, , Vladimir Stojanovi, Dejan Markovic, and Elad Alon. 2011. “Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic.” IEEE Transactions on Electron Devices 58 (1): 236–50. doi:10.1109/TED.2010.2082545.