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A 133 MHz Radiation-Hardened Delay-Locked Loop.
- Source :
- IEEE Transactions on Nuclear Science; 12/1/2010 Part 1, Vol. 57 Issue 6, p3626-3633, 8p
- Publication Year :
- 2010
-
Abstract
- A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 \mum fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189499
- Volume :
- 57
- Issue :
- 6
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Nuclear Science
- Publication Type :
- Academic Journal
- Accession number :
- 57254225
- Full Text :
- https://doi.org/10.1109/TNS.2010.2086485