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Differentially-tuned low-spur PLL using 65 nm CMOS process.
- Source :
- Electronics Letters (Institution of Engineering & Technology); 3/17/2011, Vol. 47 Issue 6, p369-371, 3p, 1 Color Photograph, 3 Diagrams, 1 Graph
- Publication Year :
- 2011
-
Abstract
- A differentially-tuned LC-VCO PLL using a transformer-resonator and a loop-phase control scheme is proposed. The phase of a control path between the differential controls is adjusted to suppress spurious tones. The measured results for the proposed PLL, implemented in a CMOS 65 nm process, show operation frequencies of 3.5-5.6 GHz, phase noise of -118.5 dBc/Hz at 1 MHz offset, and spur rejection of 73 dB, while dissipating 3.2 mA at 1 V supply. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00135194
- Volume :
- 47
- Issue :
- 6
- Database :
- Complementary Index
- Journal :
- Electronics Letters (Institution of Engineering & Technology)
- Publication Type :
- Academic Journal
- Accession number :
- 59308985
- Full Text :
- https://doi.org/10.1049/el.2011.0166