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A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic.

Authors :
Abdel-Hafeez, Saleh
Gordon-Ross, Ann
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2011, Vol. 19 Issue 6, p1023-1033, 11p
Publication Year :
2011

Abstract

We present a high-speed wide-range parallel counter that achieves high operating frequencies through a novel pipeline partitioning methodology (a counting path and state look-ahead path), using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state look-ahead path, simple D-type flip-flops, and 2-bit counters. The state look-ahead path prepares the counting path's next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. The structure is scalable to arbitrary N-bit counter widths (2-to-2N range) using only the three module types and no fan-in or fan-out increase. The counter's delay is comprised of the initial module access time (a simple 2-bit counting stage), one three-input and-gate delay, and a D-type flip-flop setup-hold time. We implemented our proposed counter using a 0.15-\mum TSMC digital cell library and verified maximum operating speeds of 2 and 1.8 GHz for 8- and 17-bit counters, respectively. Finally, the area of a sample 8-bit counter was 78 125 \mum^2 (510 transistors) and consumed 13.89 mW at 2 GHz. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
10638210
Volume :
19
Issue :
6
Database :
Complementary Index
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication Type :
Academic Journal
Accession number :
60967591
Full Text :
https://doi.org/10.1109/TVLSI.2010.2044818