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Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Oct2011, Vol. 19 Issue 10, p1911-1916, 6p
- Publication Year :
- 2011
-
Abstract
- In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 19
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 64078449
- Full Text :
- https://doi.org/10.1109/TVLSI.2010.2059054