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DC-DC Buck Converter EMI Reduction Using PCB Layout Modification.
- Source :
- IEEE Transactions on Electromagnetic Compatibility; Aug2011, Vol. 53 Issue 3, p806-813, 8p
- Publication Year :
- 2011
-
Abstract
- The paper treats the effect of layout on the electromagnetic interference (EMI) of buck converters. An optimized layout design for dc-dc synchronous buck converter is proposed for EMI reduction. Six different layout versions are analyzed with respect to loop area, loop inductance, radiating dipole moments, and far-field radiation. Optimizations are done with respect to field-effect transistor (FET), decoupling capacitor and via placement. Passive full-wave simulations are used to estimate and verify the loop inductance and far-field emissions. Those are compared with measurements. A gigahertz transverse electromagnetic (GTEM) cell is used to quantify the dipole moments in the printed circuit board (PCB) for estimating the far field and comparing to measurement. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 00189375
- Volume :
- 53
- Issue :
- 3
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Electromagnetic Compatibility
- Publication Type :
- Academic Journal
- Accession number :
- 64470531
- Full Text :
- https://doi.org/10.1109/TEMC.2011.2145421