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Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Feb2012, Vol. 20 Issue 2, p361-366, 6p
- Publication Year :
- 2012
-
Abstract
- In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 10638210
- Volume :
- 20
- Issue :
- 2
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Publication Type :
- Academic Journal
- Accession number :
- 71537772
- Full Text :
- https://doi.org/10.1109/TVLSI.2010.2096483