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Timing optimization of FPGA placements by logic replication.

Authors :
Beraudo, Giancarlo
Lillis, John
Source :
DAC: Annual ACM/IEEE Design Automation Conference; Jun2003, p196-201, 6p
Publication Year :
2003

Details

Language :
English
ISSN :
0738100X
Database :
Complementary Index
Journal :
DAC: Annual ACM/IEEE Design Automation Conference
Publication Type :
Conference
Accession number :
73576842
Full Text :
https://doi.org/10.1145/775832.775885