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A 0.5-V 35- \mu W 85-dB DR Double-Sampled \Delta\Sigma Modulator for Audio Applications.

Authors :
Yang, Zhenglin
Yao, Libin
Lian, Yong
Source :
IEEE Journal of Solid-State Circuits; Mar2012, Vol. 47 Issue 3, p722-735, 14p
Publication Year :
2012

Abstract

This paper presents a 0.5-V 1.5-bit double-sampled \Delta\Sigma modulator for audio applications. Unlike existing double-sampled designs, the proposed double-sampled \Delta\Sigma modulator employs an input-feedforward topology to reduce internal signal swings, thereby relaxing design requirements for the low-voltage building blocks and reducing distortion. Moreover, in order to avoid instability and noise shaping degradation, the proposed architecture restores the noise transfer function (NTF) of the double-sampled modulator to its single-sampled equivalent with the help of compensation loops. In the circuit implementation, the proposed fully-differential amplifier adopts an inverter output stage and a common-mode feedback (CMFB) circuit with a global feedback loop in order to reduce power consumption. A resistor-string-reference switch matrix based on a direct summation quantizer is used to simplify the analog compensation loop. The chip prototype has been fabricated in a 0.13-\mum CMOS technology with a core area of 0.57 \mm^2. The measured results show that when operating from a 0.5-V supply and clocked at 1.25∼MHz, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 81.7 dB, a peak signal-to-noise ratio (SNR) of 82.4 dB and a dynamic range (DR) of 85.0 dB while consuming 35.2\ \mu\W for a 20-kHz signal bandwidth. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189200
Volume :
47
Issue :
3
Database :
Complementary Index
Journal :
IEEE Journal of Solid-State Circuits
Publication Type :
Academic Journal
Accession number :
73739863
Full Text :
https://doi.org/10.1109/JSSC.2011.2181677