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Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes.

Authors :
Wong, M. M.
Wong, M. L. D.
Nandi, A. K.
Hijazin, I.
Source :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Jun2012, Vol. 20 Issue 6, p1151-1155, 5p
Publication Year :
2012

Abstract

In this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field GF(((2^2)^2)^2). The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
10638210
Volume :
20
Issue :
6
Database :
Complementary Index
Journal :
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication Type :
Academic Journal
Accession number :
75166570
Full Text :
https://doi.org/10.1109/TVLSI.2011.2141693