Exploiting Die-to-Die Thermal Coupling in 3D IC Placement.

In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce the local power den- sity and vertically aligned across dies simultaneously to increase thermal conductivity to the heatsink. Second, we move high-power logic cells to the location that has higher conductivity to the heatsink while moving TSVs in the upper dies so that high-power cells are vertically overlapping below the TSVs. These methods are em- ployed in a force-directed 3D placement successfully and outper- form several state-of-the-art placers published in recent literature. [ABSTRACT FROM AUTHOR]