A Parallel Simulated Annealing Approach for Floorplanning in VLSI.

One of the critical issues in floorplanning is to minimize area and/or wire length of a given design with millions of transistors while considering other factors which may influence the success of design flow or even manufacturing. To deal with the floorplan design with enormous amount of interconnections and design blocks, we adopt a parallel computing environment to increase the throughput of solution space searching. Also, we include the fractional factorial analysis to further reduce the time needed to search the acceptable solution. The experimental results indicate that our approach can obtain better space utility rate and it takes less time than the traditional method and parallel method do. [ABSTRACT FROM AUTHOR]