A Novel Graphical Based Tool for Extraction of Magnetic Reluctances Between On-Chip Current Loops.

Continued device scaling into the nanometer region has given rise to new effects that previously had negligible impact but now present greater challenges and unprecedented complexity to designing successful mixed-signal silicon. This paper presents a novel graphical tool for semi automatic extraction of magnetic reluctances between on-chip current loops. The novel graphical tool seamlessly integrates within the workflow of the CHAMELEON-RF software prototype developed. [ABSTRACT FROM AUTHOR]