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A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.

Authors :
Lee, Ja-Yol
Park, Mi-Jeong
Min, Byung-Hun
Kim, Seongdo
Park, Mun-Yang
Yu, Hyun-Kyu
Source :
IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Aug2012, Vol. 59 Issue 8, p1706-1719, 14p
Publication Year :
2012

Abstract

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97∼dBc in-band phase noise, - 38∼dBc/Hz integrated noise, and 740 ns settling time. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
15498328
Volume :
59
Issue :
8
Database :
Complementary Index
Journal :
IEEE Transactions on Circuits & Systems. Part I: Regular Papers
Publication Type :
Periodical
Accession number :
79680187
Full Text :
https://doi.org/10.1109/TCSI.2012.2206500