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A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.

Authors :
Elshazly, A.
Inti, R.
Wenjing Yin
Young, B.
Hanumolu, P.K.
Source :
2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2011, p92-94, 3p
Publication Year :
2011

Details

Language :
English
ISBNs :
9781612843032
Database :
Complementary Index
Journal :
2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Publication Type :
Conference
Accession number :
80397902
Full Text :
https://doi.org/10.1109/ISSCC.2011.5746233