An 8MB level-3 cache in 32nm SOI with column-select aliasing.

Authors :: Weiss, D.
Dreesen, M.
Ciraula, M.
Henrion, C.
Helt, C.
Freese, R.
Miles, T.
Karegar, A.
Schreiber, R.
Schneller, B.
Wuu, J.
Source :: 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2011, p258-260, 3p
Publication Year :: 2011

Language :: English
ISBNs :: 9781612843032
Database :: Complementary Index
Journal :: 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Publication Type :: Conference
Accession number :: 80397978
Full Text :: https://doi.org/10.1109/ISSCC.2011.5746309