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Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics.

Authors :
Chiarella, T.
Ramos, J.
Nackaerts, A.
Demuynck, S.
Verhaegen, S.
Verbeeck, R.
de Potter de ten Broeck, M.
Kerner, C.
Hoffmann, T.
Van Hove, M.
Debusschere, I.
Biesemans, S.
Source :
2006 IEEE International Conference on Microelectronic Test Structures; 2006, p93-97, 5p
Publication Year :
2006

Details

Language :
English
ISBNs :
9781424401673
Database :
Complementary Index
Journal :
2006 IEEE International Conference on Microelectronic Test Structures
Publication Type :
Conference
Accession number :
80832856
Full Text :
https://doi.org/10.1109/ICMTS.2006.1614282