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Scalable Gate-Level Models for Power and Timing Analysis.

Authors :
Badaroglu, M.
Van der Plas, G.
Wambacq, P.
Donnay, S.
Gielen, G.
De Man, H.
Source :
2007 IEEE International Symposium on Circuits & Systems; 2007, p2938-2941, 4p
Publication Year :
2007

Details

Language :
English
ISBNs :
9781424409204
Database :
Complementary Index
Journal :
2007 IEEE International Symposium on Circuits & Systems
Publication Type :
Conference
Accession number :
80913247
Full Text :
https://doi.org/10.1109/ISCAS.2007.377865
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