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Thermal resistance reduction in power MOSFETs integrated in a 65nm SOI technology.

Authors :
Bon, O.
Roig, J.
Morancho, F.
Haendler, S.
Gonnard, O.
Raynaud, C.
Source :
ESSDERC 2007 - 37th European Solid State Device Research Conference; 2007, p171-174, 4p
Publication Year :
2007

Details

Language :
English
ISBNs :
9781424411238
Database :
Complementary Index
Journal :
ESSDERC 2007 - 37th European Solid State Device Research Conference
Publication Type :
Conference
Accession number :
81133100
Full Text :
https://doi.org/10.1109/ESSDERC.2007.4430906