Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process.

MLA

Summerfelt, S., et al. “Embedded Ferroelectric Memory Using a 130-Nm 5 Metal Layer Cu / FSG Logic Process.” Proceedings 2004 IEEE Computational Systems Bioinformatics Conference, Jan. 2004, pp. 153–54. EBSCOhost, https://doi.org/10.1109/NVMT.2004.1380833.

APA

Summerfelt, S., Aggarwal, S., Boku, K., Celii, F., Hall, L., Matz, L., Martin, S., McAdams, H., Remack, K., Rodriguez, J., Taylor, K., Udayakumar, K. R., Moise, T., Bailey, R., Depner, M., Fox, G., & Eliason, J. (2004). Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process. Proceedings 2004 IEEE Computational Systems Bioinformatics Conference, 153–154. https://doi.org/10.1109/NVMT.2004.1380833

Chicago

Summerfelt, S., S. Aggarwal, K. Boku, F. Celii, L. Hall, L. Matz, S. Martin, et al. 2004. “Embedded Ferroelectric Memory Using a 130-Nm 5 Metal Layer Cu / FSG Logic Process.” Proceedings 2004 IEEE Computational Systems Bioinformatics Conference, January, 153–54. doi:10.1109/NVMT.2004.1380833.