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A fast hardware/software co-verification method for systern-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.

Authors :
Nakamura, Y.
Hosokawa, K.
Kuroda, I.
Ko Yoshikawa
Yoshimura, T.
Source :
Proceedings 41st Design Automation Conference, 2004; 2004, p299-304, 6p
Publication Year :
2004

Details

Language :
English
ISBNs :
9781511838283
Database :
Complementary Index
Journal :
Proceedings 41st Design Automation Conference, 2004
Publication Type :
Conference
Accession number :
81262667
Full Text :
https://doi.org/10.1109/DAC.2004.240325