A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch.

Authors :: Basker, V.S.
Standaert, T.
Kawasaki, H.
Yeh, C.
Maitra, K.
Yamashita, T.
Faltermeier, J.
Adhikari, H.
Jagannathan, H.
Wang, J.
Sunamura, H.
Kanakasabapathy, S.
Schmitz, S.
Cummings, J.
Inada, A.
Lin, C.
Kulkarni, P.
Zhu, Y.
Kuss, J.
Yamamoto, T.
Source :: 2010 Symposium on VLSI Technology (VLSIT); 2010, p19-20, 2p
Publication Year :: 2010

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