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Simulation of off-state degradation at high temperature in High Voltage NMOS transistor with STI architecture.

Authors :
Bach, S.
Borella, F.
Cambieri, J.
Pizzo, G.
Causio, A.
Atzeni, L.
Riccardi, D.
Zullino, L.
Croce, G.
Nannipieri, A.
Source :
2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD); 2010, p189-192, 4p
Publication Year :
2010

Details

Language :
English
ISBNs :
9781424477180
Database :
Complementary Index
Journal :
2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD)
Publication Type :
Conference
Accession number :
81646863

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