An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits.

MLA

Sawicki, S., et al. “An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits.” 2006 49th IEEE International Midwest Symposium on Circuits & Systems, Jan. 2006, pp. 699–703. EBSCOhost, https://doi.org/10.1109/MWSCAS.2006.381827.

APA

Sawicki, S., Hentschke, R., Johann, M., & Reis, R. (2006). An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits. 2006 49th IEEE International Midwest Symposium on Circuits & Systems, 699–703. https://doi.org/10.1109/MWSCAS.2006.381827

Chicago

Sawicki, S., R. Hentschke, M. Johann, and R. Reis. 2006. “An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits.” 2006 49th IEEE International Midwest Symposium on Circuits & Systems, January, 699–703. doi:10.1109/MWSCAS.2006.381827.