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Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays.

Authors :
Ansaloni, Giovanni
Tanimura, Kazuyuki
Pozzi, Laura
Dutt, Nikil
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Dec2012, Vol. 31 Issue 12, p1803-1816, 14p
Publication Year :
2012

Abstract

Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than state-of-the-art approaches (as much as 38% for the benchmark applications considered). [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02780070
Volume :
31
Issue :
12
Database :
Complementary Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
83467213
Full Text :
https://doi.org/10.1109/TCAD.2012.2209886