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A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit.
- Source :
- 7th International Symposium on Quality Electronic Design (ISQED'06); Mar2006, p813-817, 5p
- Publication Year :
- 2006
Details
- Language :
- English
- ISBNs :
- 9780769525235
- Database :
- Complementary Index
- Journal :
- 7th International Symposium on Quality Electronic Design (ISQED'06)
- Publication Type :
- Conference
- Accession number :
- 84113148
- Full Text :
- https://doi.org/10.1109/ISQED.2006.9