Cite
Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects.
MLA
Lee, Kyeong-Jae, et al. “Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects.” IEEE Transactions on Electron Devices, vol. 60, no. 1, Jan. 2013, pp. 383–90. EBSCOhost, https://doi.org/10.1109/TED.2012.2225150.
APA
Lee, K.-J., Park, H., Kong, J., & Chandrakasan, A. P. (2013). Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects. IEEE Transactions on Electron Devices, 60(1), 383–390. https://doi.org/10.1109/TED.2012.2225150
Chicago
Lee, Kyeong-Jae, Hyesung Park, Jing Kong, and Anantha P. Chandrakasan. 2013. “Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects.” IEEE Transactions on Electron Devices 60 (1): 383–90. doi:10.1109/TED.2012.2225150.