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A 6.0–13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Jan2013, Vol. 60 Issue 1, p108-115, 8p
- Publication Year :
- 2013
-
Abstract
- A 6.0–13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 60
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 84675106
- Full Text :
- https://doi.org/10.1109/TCSI.2012.2215696