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Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-V \rm T Operation.
- Source :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Dec2012, Vol. 59 Issue 12, p913-917, 5p
- Publication Year :
- 2012
-
Abstract
- Techniques are evaluated for implementing error correction codes in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed, and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub-VT implementation is predicted to offer 29\times gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital implementation of the same design. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 15497747
- Volume :
- 59
- Issue :
- 12
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part II: Express Briefs
- Publication Type :
- Academic Journal
- Accession number :
- 85276969
- Full Text :
- https://doi.org/10.1109/TCSII.2012.2231040