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A 10Gb/s 10mW 2-tap reconfigurable pre-emphasis transmitter in 65nm LP CMOS.
- Source :
- Proceedings of the IEEE 2012 Custom Integrated Circuits Conference; 1/ 1/2012, p1-4, 4p
- Publication Year :
- 2012
-
Abstract
- A low-power pre-emphasis voltage mode transmitter architecture with output swing control, pre-emphasis coefficient control, and online impedance calibration is proposed and demonstrated. A 65nm LP CMOS implementation of this architecture dissipates only ∼10mW from a 1.2V supply when transmitting 10Gb/s 400mV differential peak-to-peak data with 2-tap pre-emphasis, achieving 1pJ/bit energy efficiency. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISBNs :
- 9781467315555
- Database :
- Complementary Index
- Journal :
- Proceedings of the IEEE 2012 Custom Integrated Circuits Conference
- Publication Type :
- Conference
- Accession number :
- 86629766
- Full Text :
- https://doi.org/10.1109/CICC.2012.6330581