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3-D Stacking of Ultrathin Chip Packages: An Innovative Packaging and Interconnection Technology.
- Source :
- IEEE Transactions on Components, Packaging & Manufacturing Technology; Jul2013, Vol. 3 Issue 7, p1114-1122, 9p
- Publication Year :
- 2013
-
Abstract
- In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3-D assembly. In this field, we present a technology for stacking multiple chip packages, resulting in total volume almost equal to that of a single bare die. The technology is based on batch-processed ultrathin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package technology enables stacking of UTCPs by vacuum lamination, followed by through-hole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 21563950
- Volume :
- 3
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Components, Packaging & Manufacturing Technology
- Publication Type :
- Academic Journal
- Accession number :
- 89023223
- Full Text :
- https://doi.org/10.1109/TCPMT.2012.2234830