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A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
- Source :
- 1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC; 1996, p376-377, 2p
- Publication Year :
- 1996
Details
- Language :
- English
- ISBNs :
- 9780780331365
- Database :
- Complementary Index
- Journal :
- 1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC
- Publication Type :
- Conference
- Accession number :
- 92110824
- Full Text :
- https://doi.org/10.1109/ISSCC.1996.488724