A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.

MLA

Nitta, Y., et al. “A 1.6 GB/s Data-Rate 1 Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture.” 1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC, Jan. 1996, pp. 376–77. EBSCOhost, https://doi.org/10.1109/ISSCC.1996.488724.

APA

Nitta, Y., Sakashita, N., Shimomura, K., Okuda, F., Shimano, H., Yamakawa, S., Furukawa, A., Kise, K., Watanabe, H., Toyoda, Y., Fukada, T., Hasegawa, M., Tsukude, M., Arimoto, K., Baba, S., Tomita, Y., Komori, S., Kyuma, K., & Abe, H. (1996). A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. 1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC, 376–377. https://doi.org/10.1109/ISSCC.1996.488724

Chicago

Nitta, Y., N. Sakashita, K. Shimomura, F. Okuda, H. Shimano, S. Yamakawa, A. Furukawa, et al. 1996. “A 1.6 GB/s Data-Rate 1 Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture.” 1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC, January, 376–77. doi:10.1109/ISSCC.1996.488724.