A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM.

Details

Language :

English

ISBNs :

9780780335417

Database :

Complementary Index

Journal :

Proceedings International Test Conference 1996 Test & Design Validity

Publication Type :

Conference

Accession number :

92251068

Full Text :

https://doi.org/10.1109/TEST.1996.556977