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A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture.

Authors :
Makino, H.
Nakase, Y.
Shinohara, H.
Source :
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93; 1993, p202-205, 4p
Publication Year :
1993

Details

Language :
English
ISBNs :
9780818642302
Database :
Complementary Index
Journal :
Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93
Publication Type :
Conference
Accession number :
92260661
Full Text :
https://doi.org/10.1109/ICCD.1993.393380