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A 4-bit/spl times/4-bit multiplier and 3-bit counter in Josephson threshold logic.
- Source :
- IEEE Journal of Solid-State Circuits; 1987, Vol. 22 Issue 4, p606-612, 7p
- Publication Year :
- 1987
Details
- Language :
- English
- ISSN :
- 00189200
- Volume :
- 22
- Issue :
- 4
- Database :
- Complementary Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Academic Journal
- Accession number :
- 92811756
- Full Text :
- https://doi.org/10.1109/JSSC.1987.1052778