A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ.

MLA

Watanabe, Y., et al. “A 286 Mm/Sup 2/ 256 Mb DRAM with /Spl Times/32 Both-Ends DQ.” IEEE Journal of Solid-State Circuits, vol. 31, no. 4, Jan. 1996, pp. 567–74. EBSCOhost, https://doi.org/10.1109/4.499734.

APA

Watanabe, Y., Hing Wong, Kirihata, T., Kato, D., DeBrosse, J. K., Hara, T., Yoshida, M., Mukai, H., Quader, K. N., Nagai, T., Poechmueller, P., Pfefferl, P., Wordeman, M. R., & Fujii, S. (1996). A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ. IEEE Journal of Solid-State Circuits, 31(4), 567–574. https://doi.org/10.1109/4.499734

Chicago

Watanabe, Y., Hing Wong, T. Kirihata, D. Kato, J.K. DeBrosse, T. Hara, M. Yoshida, et al. 1996. “A 286 Mm/Sup 2/ 256 Mb DRAM with /Spl Times/32 Both-Ends DQ.” IEEE Journal of Solid-State Circuits 31 (4): 567–74. doi:10.1109/4.499734.