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Experimental 0.25-/spl mu/m-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique.

Authors :
Ohno, T.
Kado, Y.
Harada, M.
Tsuchiya, T.
Source :
IEEE Transactions on Electron Devices; 1995, Vol. 42 Issue 8, p1481-1486, 6p
Publication Year :
1995

Details

Language :
English
ISSN :
00189383
Volume :
42
Issue :
8
Database :
Complementary Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
93119857
Full Text :
https://doi.org/10.1109/16.398663