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A New Error Correction Circuit for Delay Locked Loops.

Authors :
Maillard, Pierre
Holman, W. Timothy
Loveless, T. Daniel
Massengill, Lloyd W.
Source :
IEEE Transactions on Nuclear Science; Dec2013 Part 1, Vol. 60 Issue 6, p4387-4393, 7p
Publication Year :
2013

Abstract

A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100~\MeV\-\cm^2/\mg show that the ECC mitigates missing pulses in DLLs fabricated at features sizes down to 40 nm and operating frequencies up to 1 GHz. In addition, any ion strike within the error correction logic components will have no significant impact on the DLL output signal. Emulated results obtained through an FPGA implementation of the ECC demonstrate the effectiveness and portability of the hardening technique. [ABSTRACT FROM PUBLISHER]

Details

Language :
English
ISSN :
00189499
Volume :
60
Issue :
6
Database :
Complementary Index
Journal :
IEEE Transactions on Nuclear Science
Publication Type :
Academic Journal
Accession number :
93280955
Full Text :
https://doi.org/10.1109/TNS.2013.2288103