Back to Search
Start Over
A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Dec2013, Vol. 60 Issue 12, p3145-3151, 7p
- Publication Year :
- 2013
-
Abstract
- An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mum CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm^2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz. [ABSTRACT FROM PUBLISHER]
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 60
- Issue :
- 12
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 95452055
- Full Text :
- https://doi.org/10.1109/TCSI.2013.2265975