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High-Throughput Cognitive-Amplification Detector for LDPC Decoders.
- Source :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Oct2014, Vol. 61 Issue 10, p2961-2969, 9p
- Publication Year :
- 2014
-
Abstract
- With the advent of technology over the recent years, the low-density parity-check (LDPC) codes, which were once seen as an impractical concept, are now poised to be the next big thing in the communication standards of today for their near-capacity performances. Nonetheless, the physical implementation of LDPC decoders is more often than not encumbered by the arithmetic of its decoding algorithm. Entangled by numerous computations of minima, LDPC decoders not only require considerable amount of resources to the implement cascaded pair-wise comparators, but also yield low decoding throughputs. In this paper, we propound a novel design for the computation of minimum and subminimum in LDPC decoding, known as the cognitive-amplification detector (CAD). By leveraging on the finite precision of fixed-point binary representation in actual hardware, our CAD proposition renders significant gains in decoding throughput and savings in resource consumption of up to 20% and 15%, respectively, not to mention negligible trade-offs in error-correcting capabilities. [ABSTRACT FROM AUTHOR]
- Subjects :
- DETECTORS
ELECTRONIC amplifiers
DECODERS (Electronics)
COMPUTERS
ARITHMETIC
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 61
- Issue :
- 10
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 98573237
- Full Text :
- https://doi.org/10.1109/TCSI.2014.2333674