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Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip.
- Source :
- Procedia Computer Science; 2015, Vol. 56, p409-414, 6p
- Publication Year :
- 2015
-
Abstract
- Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=log n 4 -2 and k>0, in worst case to determine the next node along the shortest path. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 18770509
- Volume :
- 56
- Database :
- Supplemental Index
- Journal :
- Procedia Computer Science
- Publication Type :
- Academic Journal
- Accession number :
- 108678258
- Full Text :
- https://doi.org/10.1016/j.procs.2015.07.228