A New SRAM Cell Design for Nano-Scale Technology.

Power consumption is becoming a pressing issue in SRAM cell design. Recent research shows that SRAM power contributes a key part of the whole chip power consumption. In this paper, we present a new 6T-SRAM cell structure for nano-scale technology with stability of low power application by using separate write and read operation. Simulation results with standard 65nm CMOS technology show the correct operation, the speed is closed to the traditional 6T cell, power consumption reduces about 22.45 % during write 0. In particular, this structure maintains its data with leakage current and positive feedback in idle mode which can greatly improve the power consumption of the nano-scale SRAM. [ABSTRACT FROM AUTHOR]