Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features

We have studied the integration process and the electrical properties of TiN/metal gate transistors with high k dielectrics for various strained substrates: Strained SOI, Strained SiGeOI, and Strained Ge. Substrate approaches enable (i)higher strain levels (additive with process induced strain), (ii)the co-integration of opposite strained layers for nMOS and PMOS, (iii)VT engineering for metal gates. Those features make the substrate approach a very promising solution for ultimate CMOS integration.