256-Mb DRAM circuit technologies for file applications

MLA

Kitsukawa, G., et al. “256-Mb DRAM Circuit Technologies for File Applications.” IEEE Journal of Solid-State Circuits, vol. 28, no. 11, Nov. 1993, pp. 1105–13. EBSCOhost, https://doi.org/10.1109/4.245589.

APA

Kitsukawa, G., Horiguchi, M., Kawajiri, Y., Kawahara, T., Akiba, T., Kawase, Y., Tachibana, T., Sakai, T., Aoki, M., Shukuri, S., Sagara, K., Nagai, R., Ohji, Y., Hasegawa, N., Yokoyama, N., Kisu, T., Yamashita, H., Kure, T., & Nishida, T. (1993). 256-Mb DRAM circuit technologies for file applications. IEEE Journal of Solid-State Circuits, 28(11), 1105–1113. https://doi.org/10.1109/4.245589

Chicago

Kitsukawa, G., M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y. Kawase, T. Tachibana, et al. 1993. “256-Mb DRAM Circuit Technologies for File Applications.” IEEE Journal of Solid-State Circuits 28 (11): 1105–13. doi:10.1109/4.245589.