Thermal Conductivity Model to Analyze the Thermal Implications in Nanowire FETs

In this article, a thermal conductivity (<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula>) model is proposed (i.e., dependent on the temperature, thickness, and doping concentration) for investigating the thermal behavior of silicon-on-insulator (SOI)-based devices. The proposed model is less complex in calculating the thermal conductivity (<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula>) compared to the existing model because the analysis of the existing model is complicated due to multiple equations. The proposed model is also easier to implement in the TCAD simulator than the existing model, which is currently being used in the Sentaurus TCAD electrothermal module to study the thermal behavior of the devices. The thermal conductivity (<inline-formula> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula>) predictions are analyzed using the proposed model, which agrees with the reported experimental data and existing complex analytical models. The thermal behavior of junctionless nanowire (JL-NW) FET is investigated using the sub-5-nm technology node-based physical parameters. It is observed that the thermal behavior depends on the temperature, thickness, and doping concentrations of the SOI devices. The proposed model provides an insightful and accurate analysis of the behavior of the SOI-based nanodimension transistors.