Integration Challenges and Options of Replacement High-κ/Metal Gate Technology for (Sub-)22nm Technology Nodes

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), focusing on the scalability challenges faced by: 1) effective work function (EWF) engineering targeting logic high-performance and low-power applications; 2) low-resistance fill-gate metallization for extremely scaled gates with high aspect-ratios; and 3) ultra-thin EOT gate dielectrics with controlled JG, reliability and variability. Also addressed is the need for, and exploration of options compatible with 3D-architecture devices (FinFETs). Key results include controlled TiN/TiAl-alloying and conformal ALD-TiN/TaSiAl for low-threshold voltage (VT) scaled NMOS, W vs.Co-Al alloy evaluation as fill-metal, and cubic-phase HfO2with higher k-value (k=30) showing improved performance and reliability when normalized to JG. Reduction of the bulk high-k dielectric defects, by implementation of an optimized post high-k deposition anneal (PDA), is shown to play a key and dominant role to enable substantial NBTI lifetime improvement in the (sub-)1nm EOT regime.