Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

The passivation of the III-V/high-k interface is of key importance in order to bring these materials into the 7 nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons and therefore the mobility will drop and the SS (Subthreshold Slope) will degrade. Additional defects present in the oxide near the III-V interface will generate device instabilities: the targeted amount of oxide traps should be below <1.5E10 /cm2at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5 nm). However, the oxide trap behavior seems to change only slightly with the ALD process and further improvement of the ALD process is required when introducing the III-V materials into the 7 nm technology node.