Characterization of Gate-Oxide Degradation Location for SiC MOSFETs Based on the Split C–V Method Under Bias Temperature Instability Conditions

Gate-oxide degradation has been one of the major reliability challenges of SiC <sc>mosfet</sc>s. Comprehensive and accurate localization of gate-oxide degradation under bias temperature instability (BTI) conditions is important to improve the device reliability. The split C–V [gate–source capacitance C_GS (v_G) and gate–drain capacitance C_GD (v_G)] method is proposed in this article to locate gate-oxide degradation. Moreover, a BTI automated characterization system integrated I–V and split C–V test is presented. The effect of gate-oxide degradation on threshold voltage and split C–V under dc and ac BTI conditions is investigated and the degradation location is analyzed. Furthermore, the degradation simulation is conducted with technology computer aided design (TCAD) to reveal the mechanism. The results show that the different parts of split C–V can characterize degradation location, the type, and energy level of traps. The acceptor traps near valence band and donor traps near conduction band cause gate-oxide degradation above the channel and junction field effect transistor (JFET) region in positive bias temperature instability (PBTI) and Negative Bias Temperature Instability (NBTI), respectively. In ac BTI, the gate-oxide degradation at the channel region is independent of v_G polarity, while the opposite is true above JFET region. These findings help to improve the long-term operation reliability of gate oxide from the perspective of chip design and application.